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authorChristian Gelinek <cgelinek@radlogic.com.au>2022-03-31 15:19:38 +1030
committerEfraim Flashner <efraim@flashner.co.il>2022-03-31 18:22:58 +0300
commit9f82d1f1c061d92cd7d7eff8a98bd8a8de99858d (patch)
treeff85ca1b42e78b918f687097e80cf9c2c02d7239
parent58874999c9809f95c220377ac3703e482f323861 (diff)
gnu: iverilog: Add zlib dependency for LXT dump file format support.
* gnu/packages/fpga.scm (iverilog)[native-inputs]: Add zlib. Signed-off-by: Efraim Flashner <efraim@flashner.co.il>
-rw-r--r--gnu/packages/fpga.scm3
1 files changed, 2 insertions, 1 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index 3b2938aff0..b8f98ca63e 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -5,6 +5,7 @@
;;; Copyright © 2019 Amin Bandali <bandali@gnu.org>
;;; Copyright © 2020 Vinicius Monego <monego@posteo.net>
;;; Copyright © 2021 Andrew Miloradovsky <andrew@interpretmath.pw>
+;;; Copyright © 2022 Christian Gelinek <cgelinek@radlogic.com.au>
;;;
;;; This file is part of GNU Guix.
;;;
@@ -111,7 +112,7 @@ formal verification.")
(arguments
`(#:make-flags (list (string-append "CC=" ,(cc-for-target)))))
(native-inputs
- (list flex bison ghostscript)) ; ps2pdf
+ (list flex bison ghostscript zlib)) ; ps2pdf
(home-page "http://iverilog.icarus.com/")
(synopsis "FPGA Verilog simulation and synthesis tool")
(description "Icarus Verilog is a Verilog simulation and synthesis tool.