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authorTobias Geerinckx-Rice <me@tobias.gr>2019-11-03 17:23:28 +0100
committerTobias Geerinckx-Rice <me@tobias.gr>2019-11-03 18:27:21 +0100
commit922c84867ae15a55e3ab3b5060afa50959bce99e (patch)
treed47fb4d8387a119d0f6126fb493b2522a826693d /gnu/packages/fpga.scm
parent1ae28a35e942dd1df0cfc8b8a73a94ef8df16d20 (diff)
gnu: yosys: Update to 0.9.
* gnu/packages/fpga.scm (yosys): Update to 0.9.
Diffstat (limited to 'gnu/packages/fpga.scm')
-rw-r--r--gnu/packages/fpga.scm4
1 files changed, 2 insertions, 2 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm
index b4f259bf3a..556eae3624 100644
--- a/gnu/packages/fpga.scm
+++ b/gnu/packages/fpga.scm
@@ -120,7 +120,7 @@ For synthesis, the compiler generates netlists in the desired format.")
(define-public yosys
(package
(name "yosys")
- (version "0.8")
+ (version "0.9")
(source (origin
(method git-fetch)
(uri (git-reference
@@ -129,7 +129,7 @@ For synthesis, the compiler generates netlists in the desired format.")
(recursive? #t))) ; for the ‘iverilog’ submodule
(sha256
(base32
- "1qwbp8gynlklawzvpa4gdn2x0hs8zln0s3kxjqkhfcjfxffdcpvv"))
+ "0lb9r055h8y1vj2z8gm4ip0v06j5mk7f9zx9gi67kkqb7g4rhjli"))
(file-name (git-file-name name version))
(modules '((guix build utils)))
(snippet