diff options
author | Efraim Flashner <efraim@flashner.co.il> | 2023-05-02 12:27:14 +0300 |
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committer | Efraim Flashner <efraim@flashner.co.il> | 2023-05-02 14:32:03 +0300 |
commit | b62c9fbdd3f706f8bcf70d92807184e507603ec5 (patch) | |
tree | 2b1a16ca6c660223501246aab0c629560297c1c5 /gnu/packages/patches | |
parent | 44d70440944aa47e5f37493346e560f38907d777 (diff) |
gnu: libaio: Fix building on riscv64-linux.
* gnu/packages/linux.scm (libaio)[arguments]: When building for
riscv64-linux add a patch to account for undeclared behavior.
[native-inputs]: Add patch file, patch.
* gnu/packages/patches/libaio-riscv-test5.patch: New file.
* gnu/local.mk (dist_patch_DATA): Register it.
Diffstat (limited to 'gnu/packages/patches')
-rw-r--r-- | gnu/packages/patches/libaio-riscv-test5.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/gnu/packages/patches/libaio-riscv-test5.patch b/gnu/packages/patches/libaio-riscv-test5.patch new file mode 100644 index 0000000000..c1df41795d --- /dev/null +++ b/gnu/packages/patches/libaio-riscv-test5.patch @@ -0,0 +1,47 @@ +https://pagure.io/libaio/pull-request/23 + +From f68c69b6cbc1260a6034997d5f146e3d0a197ed8 Mon Sep 17 00:00:00 2001 +From: Xiongchuan Tan <xc-tan@outlook.com> +Date: Jun 28 2022 15:53:38 +0000 +Subject: As of June 28th, 2022, the RISC-V spec[1] reserves the PTE permission bit + +combination of "write+!read", and the kernel would have incoherent behavior in +the last test case of "harness/cases/5.t". Since it leads to undefined behavior, +until further spec update, this test case should be disabled for RISC-V. + +A patch to disallow such permission in mmap() can be found here[2]. + +[1]: https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf +[2]: https://www.spinics.net/lists/kernel/msg4412421.html + +--- + +diff --git a/harness/cases/5.t b/harness/cases/5.t +index b0a7c56..8d6c959 100644 +--- a/harness/cases/5.t ++++ b/harness/cases/5.t +@@ -37,6 +37,14 @@ int test_main(void) + status |= attempt_rw(rwfd, buf, SIZE, 0, READ, -EFAULT); + + res = munmap(buf, page_size); assert(res == 0); ++ ++ /* As of June 28th, 2022, the RISC-V spec Volume 2 Section 4.3 ++ * version "20211203 Privileged Architecture v1.12, Ratified" ++ * reserves the usage of the PTE permission bit combination of ++ * "write+!read", so the next test leads to undefined behavior ++ * and should be disabled. */ ++#ifndef __riscv ++ + buf = mmap(0, page_size, PROT_WRITE, MAP_SHARED, rwfd, 0); + assert(buf != (char *)-1); + +@@ -48,6 +56,8 @@ int test_main(void) + status |= attempt_rw(rwfd, buf, SIZE, 0, READ, SIZE); + status |= attempt_rw(rwfd, buf, SIZE, 0, WRITE, res); + ++#endif ++ + return status; + } + + |