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| author | Jakub Kądziołka <kuba@kadziolka.net> | 2020-07-23 21:43:06 +0200 |
|---|---|---|
| committer | Jakub Kądziołka <kuba@kadziolka.net> | 2020-07-23 21:43:06 +0200 |
| commit | d726b954baaeff876ce9728e00920fa45f529f9a (patch) | |
| tree | 4b767b7586a1082dd2691bc33c3e45ace044e6e5 /gnu/packages/fpga.scm | |
| parent | 9a74a7db8626bc139307d115f5cec2648f5273ad (diff) | |
| parent | e165a2492d73d37c8b95d6970d453b9d88911ee6 (diff) | |
Merge branch 'master' into core-updates
Conflicts:
gnu/packages/ruby.scm
Diffstat (limited to 'gnu/packages/fpga.scm')
| -rw-r--r-- | gnu/packages/fpga.scm | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gnu/packages/fpga.scm b/gnu/packages/fpga.scm index fda5de60c7..b2717d2233 100644 --- a/gnu/packages/fpga.scm +++ b/gnu/packages/fpga.scm @@ -127,7 +127,7 @@ For synthesis, the compiler generates netlists in the desired format.") (source (origin (method git-fetch) (uri (git-reference - (url "https://github.com/cliffordwolf/yosys.git") + (url "https://github.com/cliffordwolf/yosys") (commit (string-append "yosys-" version)) (recursive? #t))) ; for the ‘iverilog’ submodule (sha256 @@ -223,7 +223,7 @@ For synthesis, the compiler generates netlists in the desired format.") (source (origin (method git-fetch) (uri (git-reference - (url "https://github.com/cliffordwolf/icestorm.git") + (url "https://github.com/cliffordwolf/icestorm") (commit commit))) (file-name (git-file-name name version)) (sha256 @@ -304,7 +304,7 @@ FOSS FPGA place and route tool.") (source (origin (method git-fetch) (uri (git-reference - (url "https://github.com/YosysHQ/arachne-pnr.git") + (url "https://github.com/YosysHQ/arachne-pnr") (commit commit))) (file-name (git-file-name name version)) (sha256 |